`include "defines.v"
module pc_reg(
	input wire clk,
	input wire rst,
	input wire[5:0] pause, //流水线暂停信号
	output reg[31:0] pc,
	output reg ce
);
	always@(posedge clk)
		if(rst == `RstEnable) begin
			ce <= `ChipDisable;
			end
		else begin
			ce <= `ChipEnable;
			end
	always@(posedge clk)
		if(ce == `ChipDisable)
			pc <= 0;			
		else if(pause[0] == `NO_PAUSE)
			pc <= pc + 4;
			
endmodule
